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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
Rev. 02 -- 26 March 2007 Product data sheet
1. General description
The SSTUB32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7 V to 2.0 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUB32864 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH). The device supports low-power standby operation. When the reset input (RESET) is LOW, the differential input receivers are disabled, and un-driven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUB32864 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs LOW. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case the set-up time requirement for DCS would be the same as for the other Dn data inputs. The SSTUB32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96) package.
NXP Semiconductors
SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
2. Features
I I I I I I I I I I I I Configurable register supporting DDR2 Registered DIMM applications Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Meets SSTUB32864 JEDEC specification speed performance Supports up to 450 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports SSTL_18 data inputs Differential clock (CK and CK) inputs Supports LVCMOS switching levels on the control and RESET inputs Single 1.8 V supply operation (1.7 V to 2.0 V) Available in 96-ball, 13.5 mm x 5.5 mm, 0.8 mm ball pitch LFBGA package
3. Applications
I 400 MT/s to 800 MT/s DDR2 registered DIMMs without parity
4. Ordering information
Table 1. Ordering information Tamb = 0 C to +70 C. Type number Solder process Package Name SSTUB32864EC/G Pb-free (SnAgCu LFBGA96 solder ball compound) Description plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm Version SOT536-1
SSTUB32864_2
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Product data sheet
Rev. 02 -- 26 March 2007
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
5. Functional diagram
RESET
CK CK VREF DCKE
SSTUB32864
1D C1 R
QCKEA QCKEB(1)
DODT
1D C1 R
QODTA QODTB(1) QCSA QCSB(1)
DCS
1D C1 R
CSR
D1
0 1 1D C1 R Q1A Q1B(1)
002aac012
to other channels
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUB32864; 1 : 2 mode (positive logic)
SSTUB32864_2
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Product data sheet
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
6. Pinning information
6.1 Pinning
ball A1 SSTUB32864EC/G index area 123456 A B C D E F G H J K L M N P R T
002aac013
Transparent top view
Fig 2. Pin configuration for LFBGA96
1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 n.c. CK CK D8 D9 D10 D11 D12 D13 D14
2 n.c. D15 D16 n.c. D17 D18 RESET DCS CSR D19 D20 D21 D22 D23 D24 D25
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14
6 DNU Q15 Q16 DNU Q17 Q18 C0 DNU ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25
002aaa955
Fig 3. Ball mapping; 1 : 1 register (C0 = 0, C1 = 0); top view
SSTUB32864_2
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Product data sheet
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 n.c. CK CK D8 D9 D10 D11 D12 D13 D14
2 n.c. DNU DNU n.c. DNU DNU RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A
6 QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B
002aaa956
Fig 4. Ball mapping; 1 : 2 register A (C0 = 0, C1 = 1); top view
1 A B C D E F G H J K L M N P R T D1 D2 D3 D4 D5 D6 n.c. CK CK D8 D9 D10 DODT D12 D13 DCKE
2 n.c. DNU DNU n.c. DNU DNU RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A QODTA Q12A Q13A QCKEA
6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B QODTB Q12B Q13B QCKEB
002aaa957
Fig 5. Ball mapping; 1 : 2 register B (C0 = 1, C1 = 1); top view
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Product data sheet
Rev. 02 -- 26 March 2007
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NXP Semiconductors
SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
6.2 Pin description
Table 2. Symbol GND Pin description Pin Type Description ground B3, B4, D3, D4, F3, F4, ground input H3, H4, K3, K4, M3, M4, P3, P4 A4, C3, C4, E3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 A3, T3 J5 J6 H1 J1 G6, G5 G2 J2, H2
[1]
VDD
1.8 V nominal
power supply voltage
VREF ZOH ZOL CK CK C0, C1 RESET CSR, DCS D1 to D25 DODT DCKE Q1 to Q25, Q1A to Q14A, Q1B to Q14B QCS, QCSA, QCSB QODT, QODTA, QODTB QCKE, QCKEA, QCKEB n.c. DNU
0.9 V nominal input input
input reference voltage reserved for future use reserved for future use
differential input positive master clock input differential input negative master clock input LVCMOS inputs configuration control inputs LVCMOS input SSTL_18 input SSTL_18 input SSTL_18 input SSTL_18 input 1.8 V CMOS Asynchronous reset input (active LOW). Resets registers and disables VREF data and clock differential-input receivers. Chip select inputs (active LOW). Disables data outputs switching when both inputs are HIGH.[2] Data inputs. Clocked in on the crossing of the rising edge of CK and the falling edge of CK. The outputs of this register will not be suspended by DCS and CSR control. The outputs of this register will not be suspended by DCS and CSR control. outputs that are suspended by DCS and CSR control[3]
[1]
[1]
[1]
[1]
1.8 V CMOS 1.8 V CMOS 1.8 V CMOS -
data outputs that will not be suspended by DCS and CSR control data outputs that will not be suspended by DCS and CSR control data outputs that will not be suspended by DCS and CSR control Not connected. Ball present but no internal connection to the die. Do-not-use. Ball internally connected to the die which should be left open-circuit.
[1]
[1]
A2, D2, G1
[1]
[1] [2]
Depends on configuration. See Figure 3, Figure 4, and Figure 5 for ball number. Configurations: Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0. Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1. Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1. Configurations: Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0. Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1. Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
[3]
SSTUB32864_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 26 March 2007
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
7. Functional description
7.1 Function table
Table 3. Function table (each flip-flop) L = LOW voltage level; H = HIGH voltage level; X = don't care; = LOW-to-HIGH transition; = HIGH-to-LOW transition Inputs RESET DCS CSR CK CK Dn, DODT, DCKE L H X L H X L H X L H X X or floating Qn Outputs[1] QCS QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L
H H H H H H H H H H H H L
[1]
L L L L L L H H H H H H X or floating
L L L H H H L L L H H H X or floating
L or H L or H L or H L or H X or floating
L or H L or H L or H L or H X or floating
L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L
L L Q0 L L Q0 H H Q0 H H Q0 L
Q0 is the previous state of the associated output.
SSTUB32864_2
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Product data sheet
Rev. 02 -- 26 March 2007
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI VO IIK IOK IO ICCC Tstg
[1] [2]
Parameter supply voltage input voltage output voltage input clamping current output clamping current output current continuous current through each VDD or GND pin storage temperature
Conditions receiver driver VI < 0 V or VI > VDD VO < 0 V or VO > VDD continuous; 0 V < VO < VDD
Min -0.5 -0.5[1] -0.5[1] -65
Max +2.5 +2.5[2] VDD + 0.5[2] 50 50 50 100 +150
Unit V V V mA mA mA mA C
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 2.5 V maximum.
9. Recommended operating conditions
Table 5. Symbol VDD Vref VT VI VIH(AC) VIL(AC) VIH(DC) VIL(DC) VIH VIL VICR VID IOH IOL Tamb
[1] [2]
Operating conditions Parameter supply voltage reference voltage termination voltage input voltage AC HIGH-level input voltage data inputs (Dn), CSR AC LOW-level input voltage DC LOW-level input voltage HIGH-level input voltage LOW-level input voltage data inputs (Dn), CSR data inputs (Dn), CSR RESET, Cn RESET, Cn
[1] [1] [2]
Conditions
Min 1.7 0.49 x VDD Vref - 0.040 0 Vref + 0.250 Vref + 0.125 0.65 x VDD 0.675 600 -
Typ 0.50 x VDD Vref -
Max 2.0 0.51 x VDD Vref + 0.040 VDD Vref - 0.250 Vref - 0.125 VDD 0.35 x VDD 1.125 -8 8 +70
Unit V V V V V V V V V V V mV mA mA C
DC HIGH-level input voltage data inputs (Dn), CSR
common mode input voltage CK, CK range differential input voltage HIGH-level output current LOW-level output current ambient temperature operating in free air CK, CK
[2]
0
The RESET and Cn inputs of the device must be held at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW.
SSTUB32864_2
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Product data sheet
Rev. 02 -- 26 March 2007
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
10. Characteristics
Table 6. Characteristics Recommended operating conditions; Tamb = 0 C to +70 C; all voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol VOH VOL II IDD Parameter HIGH-level output voltage LOW-level output voltage input current supply current Conditions IOH = -6 mA; VDD = 1.7 V IOL = 6 mA; VDD = 1.7 V all inputs; VI = VDD or GND; VDD = 2.0 V static Standby mode; RESET = GND; IO = 0 mA; VDD = 2.0 V static Operating mode; RESET = VDD; IO = 0 mA; VDD = 2.0 V; VI = VIH(AC) or VIL(AC) IDDD dynamic operating current per MHz clock only; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. IO = 0 mA; VDD = 2.0 V per each data input, 1 : 1 mode; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 2.0 V per each data input, 1 : 2 mode; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 2.0 V Ci input capacitance data inputs, CSR; VI = Vref 250 mV; VDD = 1.8 V CK and CK; VICR = 0.9 V; VID = 600 mV; VDD = 1.8 V RESET; VI = VDD or GND; VDD = 1.8 V Min 1.2 -5 Typ Max 0.5 +5 2 Unit V V A mA
-
-
40
mA
-
16
-
A
-
11
-
A
-
19
-
A
2.5 2 2
-
3.5 3 4
pF pF pF
SSTUB32864_2
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Product data sheet
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
Table 7. Timing requirements Recommended operating conditions; Tamb = 0 C to +70 C; VDD = 1.8 V 0.1 V; unless otherwise specified. See Figure 6 through Figure 11. Symbol fclock tW tACT tINACT tsu Parameter clock frequency pulse width differential inputs active time differential inputs inactive time set-up time DCS before CK , CK , CSR HIGH DCS before CK , CK , CSR LOW CSR, ODT, CKE, and data before CK , CK th hold time DCS, CSR, ODT, CKE, and data after CK , CK CK, CK HIGH or LOW
[1][2] [1][3]
Conditions
Min 1 0.6 0.5 0.5 0.4
Typ -
Max 450 10 15 -
Unit MHz ns ns ns ns ns ns ns
[1] [2] [3]
This parameter is not necessarily production tested. Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 8. Switching characteristics Recommended operating conditions; Tamb = 0 C to +70 C; VDD = 1.8 V 0.1 V; Class I, Vref = VT = VDD x 0.5 and CL = 10 pF; unless otherwise specified. See Figure 6 through Figure 11. Symbol fmax tPDM tPDMSS tPHL
[1] [2]
Parameter maximum input clock frequency peak propagation delay simultaneous switching peak propagation delay HIGH-to-LOW propagation delay
Conditions CK and CK to output CK and CK to output RESET to output
[1] [1][2]
Min 450 1.1 -
Typ -
Max 1.5 1.6 3
Unit MHz ns ns ns
Includes 350 ps of test-load transmission line delay. This parameter is not necessarily production tested.
Table 9. Output edge rates Recommended operating conditions; VDD = 1.8 V 0.1 V; unless otherwise specified. Symbol dV/dt_r dV/dt_f dV/dt_ Parameter rising edge slew rate falling edge slew rate absolute difference between dV/dt_r and dV/dt_f Conditions Min 1 1 Typ Max 4 4 1 Unit V/ns V/ns V/ns
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
11. Test information
11.1 Test circuit
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified. The outputs are measured one at a time with one transition per measurement.
VDD DUT
50
CK inputs
CK CK test point
RL = 100
delay = 350 ps Zo = 50
RL = 1000
OUT
CL = 30 pF(1) RL = 1000
test point
002aaa371
(1) CL includes probe and jig capacitance.
Fig 6. Load circuit
LVCMOS RESET 0.5VDD tINACT IDD(1) 0.5VDD
VDD 0V tACT 90 % 10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 7. Voltage and current waveforms; inputs active and inactive times
tW VIH input VICR VICR VID VIL
002aaa373
VID = 600 mV. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 8. Voltage waveforms; pulse duration
SSTUB32864_2
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Product data sheet
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
CK VICR CK tsu input Vref th VIH Vref VIL
002aaa374
VID
VID = 600 mV. Vref = 0.5VDD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 9. Voltage waveforms; set-up and hold times
CK VICR CK tPLH tPHL VOH output VT VOL 002aaa375 VICR Vi(p-p)
tPLH and tPHL are the same as tPD.
Fig 10. Voltage waveforms; propagation delay times (clock to output)
LVCMOS VIH RESET 0.5VDD VIL tPHL VOH output VT VOL 002aaa376
tPLH and tPHL are the same as tPD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; propagation delay times (reset to output)
SSTUB32864_2
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
11.2 Output slew rate measurement
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V / ns 20 %, unless otherwise specified.
VDD DUT
RL = 50
OUT
CL = 10 pF(1)
test point
002aaa377
(1) CL includes probe and jig capacitance.
Fig 12. Load circuit, HIGH-to-LOW slew measurement
output 80 % dv_f 20 % dt_f
002aaa378
VOH
VOL
Fig 13. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
CL = 10 pF(1)
test point
RL = 50
002aaa379
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, LOW-to-HIGH slew measurement
dt_r VOH 80 % dv_r 20 % output
002aaa380
VOL
Fig 15. Voltage waveforms, LOW-to-HIGH slew rate measurement
SSTUB32864_2
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Product data sheet
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
D
B
A
ball A1 index area
A E
A2 A1 detail X
e1
1/2 e
C
v M C A B
e T R P N M L K J H G F E D C B A ball A1 index area
y1 C
y
b
w M C
e
e2
1/2 e
123456 X 0 5 scale 10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 13.6 13.4 e 0.8 e1 4 e2 12 v 0.15 w 0.1 y 0.1 y1 0.2
OUTLINE VERSION SOT536-1
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 00-03-04 03-02-05
Fig 16. Package outline SOT536-1 (LFBGA96)
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Product data sheet
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Product data sheet
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 11. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17.
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Product data sheet
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SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 12. Acronym CMOS DDR DIMM LVCMOS PRR RDIMM SSTL Abbreviations Description Complementary Metal Oxide Semiconductor Double Data Rate Dual In-line Memory Module Low Voltage Complementary Metal Oxide Semiconductor Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic
15. Revision history
Table 13. Revision history Release date 20070326 Data sheet status Product data sheet Change notice Supersedes SSTUB32864_1 Document ID SSTUB32864_2 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 6 "Characteristics", symbol IDD (max.) changed from "100 A" to "2 mA". Product data sheet -
SSTUB32864_1
20060421
SSTUB32864_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 26 March 2007
17 of 19
NXP Semiconductors
SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
SSTUB32864_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 26 March 2007
18 of 19
NXP Semiconductors
SSTUB32864
1.8 V configurable registered buffer for DDR2-800 RDIMM applications
18. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 11.1 11.2 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output slew rate measurement. . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction to soldering . . . . . . . . . . . . . . . . . 15 Wave and reflow soldering . . . . . . . . . . . . . . . 15 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 March 2007 Document identifier: SSTUB32864_2

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